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AN729 vishay siliconix document number: 71116 25-feb-00 www.vishay siliconix.com faxback 408-970-5600 1 designing a high-frequency, higher-power buck/boost converter for multi-cell input configurations using si9168 nitin kalje the si9168 is a high-frequency synchronous dc-to-dc controller designed for higher-power buck or boost conversion applications in end products running off 2-cell lithium ion or 6-cell nicd or nimh battery packs. like the lower-power si9167, the si9168 is capable of operating at up to 2 mhz while offering the flexibility to choose the optimum drivers for higher current handling. its high-frequency operation, strong totem pole drivers, selectable pwm/psm operation modes, integrated under-voltage lockout, and soft-start features make the si9168 suitable for 1-a to 10-a conversion applications. a synchronization feature allows designers to use multiple si9168s for a complete power management system, where size and cost are a prime importance. the si9168 is designed to promote efficient use of battery energy and to allow the use of smaller form factors, thanks to better heat dissipation and thereby lower operating junction temperature of power management components. the features and functions of the si9168 are described in detail in the product data sheet. the following section provides design guidelines for the creation of buck and boost dc-to-dc converters using the si9168. oscillator frequencyechoosing r osc the oscillator function is implemented with an rs flip-flop, an inverter, an internal capacitor, a temperature-compensated current source, and an external resistor. the oscillator ramp is generated by charging the internal capacitor with a constant current source. this current is mirrored from the current in r osc . the capacitor is charged from 0.5 v to a 1-v threshold, where it is discharged at a faster rate and the flip-flop is reset for the next cycle. the lower the value of rosc, the higher the charging current and the higher the oscillator frequency. the oscillator is guaranteed to operate within 20% with a 1% r osc for the 200-khz to 2-mhz frequency range. refer to figure 2 to set the oscillator frequency.
si9168bq v out 1.310 v sd v out v dd r osc gnd d l pwm/psm pgnd comp sync v s buck mode boost/buck v ref fb d h v in 5-10 v si9168bq v out 5-12.6 v sd v out v dd r osc gnd d l pwm/psm pgnd comp sync v s boost mode boost/buck v ref fb d h v in 5-10 v
AN729 vishay siliconix www.vishay siliconix.com faxback 408-970-5600 2 document number: 71116 25-feb-00 figure 1. reference threshold generator soft-start timer oscillator c osc uvlo por bias generator system monitor drivers pwm in psm in pwm/pfm select pwm in psm in pwm modulator psm modulator 0.5 v 1.0 v ramp v ref v o fb comp sync r osc mode pwm/psm gnd v dd sd dl negative return and substrate positive supply 1.3 v pgnd dh v s figure 2. frequency setting 100 1000 10000 10 100 1000 r osc (k )
frequency (khz) synchronization the internal single-shot circuit resets the flip-flop at the low-going edge of the external synchronization pulse. the external clock driving the synchronization pin does not get loaded because of the low input capacitance seen at the synchronous pin. at every cycle, the low-going external clock pulse would end the positive ramp and start the next cycle. obviously, the external clock frequency needs to be at least 20% higher than the internal oscillator frequency for reliable synchronization. in addition, the minimum low pulse width must be 50 ns, while the fall time should not exceed 50 ns (refer to figure 3). figure 4 shows the synchronization achieved with the external clock running at 1.2 times the internal oscillator frequency.
AN729 vishay siliconix document number: 71116 25-feb-00 www.vishay siliconix.com faxback 408-970-5600 3 figure 3. synch pulse width 50% t low 50 nsec t r , t f 50 nsec 90% 10% sync single shot oscillator r osc ch1 external clock (5 v/div) ch4 drive output (5 v/div) f osc (internal) 825 khz f clock (external) 1 mhz figure 4. synchronization duty cycle in pwm mode, the controller operates at a fixed frequency determined by r osc . the duty cycle in buck or boost mode is a function of the difference in the input and output voltage levels, with the maximum duty ratio at a minimum input line. at 2 mhz, the duty cycle in buck mode increases gradually up to a typical level of 80% before jumping instantaneously to 100%. at this time, the upper switch is continuously in the on state and the converter functions as a low dropout regulator. the difference between the input and output voltages is equal to the resistive drop in the upper mosfet switch, the inductor, and the printed circuit board (pcb) traces. since the fixed break-before-make (bbm) time causes this sudden jump, the maximum duty cycle the converter can attain before going into ldo mode will increase at lower switching frequencies. in boost mode, the same phenomenon is observed when the duty cycle needs to be reduced down to 0%. the decrease will be gradual from 75% to 5% and abrupt from 5% to 0%. the maximum duty cycle in boost mode is limited in order to provide a fixed off-state time for an inductor to discharge before the next cycle. obviously, the maximum achievable duty cycle is inversely proportional to the switching frequency of the converter. refer to figure 5 and figure 6 for typical maximum duty cycles at selected operating frequencies.
AN729 vishay siliconix www.vishay siliconix.com faxback 408-970-5600 4 document number: 71116 25-feb-00 before selecting the operating frequency, ensure that the maximum duty cycle required at the minimum input and maximum output voltages and loads is less than or equal to the maximum provided by the si9168. refer equations 1 and 2 to calculate the maximum operating duty cycle at the rated load. d maxbuck v out_max v esr v trace v in_min r ds_p i out (1) d max boost v out_max v esr v trace r ds_p i in v in_min v out_max i in r ds_p r ds_n (2) where, v esr ,v trace = dc voltage drop across inductor esr, pcb traces (v) r ds_p , r ds_n = on-resistance of p- or n- channel mosfet at an operating junction temperature ( ) v in_min , v out_max = extreme minimum input and maximum output voltage (v) i in , i out = input supply and output load currents (a) mosfet selection synchronous rectification is used to achieve the best possible efficiency at moderate to high load currents. a moderate to high load can be defined as the value at which the total voltage drop across the synch switch is less than the forward voltage drop of the schottky rectifier, which otherwise is used in asynchronous dc-dc converter. at lower loads, the switching losses of the synchronous switch can outweigh the dc losses. under such circumstances, the si9168 operates in pulse skipping mode, where it shuts off the synchronous switch driver and allows the parallel schottky diode to conduct. selection criteria for the power mosfet include on-resistance (r ds(on) ), total gate charge(q g ), rise/fall time (t r /t f ) and gate threshold (v gs(th) ). mosfet on-resistance is inversely proportional to the number of cells or the channel width, while the gate capacitance increases with the channel width. the product of the gate charge and on-resistance is thus a figure of merit, with a lower number signifying better performance. vishay offers a wide range of pwm-optimized mosfets using trench technology to provide the lowest product of on-resistance times gate charge. lower gate charge is needed to reduce cv 2 as well as cross conduction losses by reducing the rise and fall times for a given peak gate current drive. this is critical especially when operating at a higher input voltages. it is also recommended to use a high gate threshold (4.5-v) mosfet to reduce the cv 2 losses further. one good approach to selecting the appropriate level of on-resistance is to calculate the dc and total switching power losses at a load level where the converter will be operating most of the time and then choose a mosfet with dc losses equal to or less than 40% of the total dc and switching losses combined. refer to equations 3 through 10 to estimate the mosfet dc (p dc ) and switching (p sw ) power losses in buck and boost converters at a nominal line and load. 70 74 78 82 86 90 94 98 400 600 800 1000 1200 1400 1600 1800 2000 2200 max duty cycle vs. frequency (buck mode) % max duty cycle frequency (khz) v in = 7.2 v figure 5. figure 6. 42 46 50 54 58 62 66 70 74 400 600 800 1000 1200 1400 1600 1800 2000 2200 max duty cycle vs. frequency (boost mode) % max duty cycle frequency (khz) v in = 7.2 v
AN729 vishay siliconix document number: 71116 25-feb-00 www.vishay siliconix.com faxback 408-970-5600 5 buck converter p swn q gn v in f sw (3) p dcn 1.4 i rmsn r ds(on)_n (4) p swp q gp v in f sw v in i pk t r t f f sw 2 (5) p dcp 1.4 i rmsp r ds(on)_p (6) boost converter p swn q gn v o f sw v o i in t r t f 2 (7) p dcn 1.4 i rmsn r ds(on)_n (8) p swp q gp v in f sw (9) p dcp 1.4 i rmsp r ds(on)_p (10) where, r ds(on)_p , r ds(on)_n = on-resistance of the p- or n-channel mosfet at 25 c junction temperature ( ) q gn , q gp = specified total gate charge for n-, p-channel switches at v in (c) t r , t f = rise/fall time of respective switches (sec) i rms-n , i rms-p = rms currents in n-/p-channel switches (a) (see appendix) once the dc and switching losses are determined, make sure that the mosfet package can handle the power dissipation without the junction temperature going above 125 c in worst-case line/load and ambient temperature conditions. diode selection in psm operation, the synchronous switch (n-channel in buck configurations and p-channel in boost configurations) is switched off to reduce switching losses. the circuit works as a non-synchronous buck or boost converter, where the diode freewheels during the off cycle. the operating frequency in psm is kept relatively low to reduce switching losses, which means that dc losses can become significant if the parasitic body diode is used as a free wheeling diode. the use of a low forward drop schottky diode is thus recommended to achieve good efficiency results in psm operation. the other reason the parasitic body diode cannot be used as a freewheeling diode is its dynamic behavior, the effect of which becomes more significant during high frequency pwm operation. break before make is internally set at about 40 ns, to avoid any possible shoot-through during the transition time. the mosfet internal body diode, being a silicon p-n junction diode, can experience a significant reverse recovery minority carrier charge if used to conduct in the forward direction during the bbm period. the result is almost the same as shoot-through without bbm and the losses are proportional to the operating frequency. at the operating frequencies above 1 mhz, these could reduce efficiency significantly. the schottky should be chosen such that at a maximum peak inductor current, the forward drop is less than the forward breakdown of internal body diode. figure 7 and 8 shows the practical waveforms explaining the bbm. ch1 d h (p-channel drive output) (5 v/div) ch4 d l (n-channel drive output) (5 v/div) figure 7. break before make (n-channel turn on)
AN729 vishay siliconix www.vishay siliconix.com faxback 408-970-5600 6 document number: 71116 25-feb-00 ch1 d h (p-channel drive output) (5 v/div) ch4 d l (n-channel drive output) (5 v/div) figure 8. break before make (p-channel turn on) inductor and capacitor proper inductor and capacitor values should be chosen to achieve the specified input/output ripple, for a selected operating frequency. for a converter, operating at near one-megahertz switching frequency, the low esr ceramic capacitors with values as low as 10 f are good enough to achieve 10-mv p-p ripple/noise at the output. the inductor value determines the ripple current( i) in the inductor and output capacitor, for given input/output voltages and switching frequency. the total peak-to-peak output ripple is contributed by the v esr , caused by the esr of the ouptut capacitor and the v c , caused by the loss of charges from the output capacitor. equal contribution of ripple voltage from the esr and capacitance can be assumed for high frequency converters using the low esr ceramic capacitors. buck refer to equation 11 in appendix to calculate the inductance value for a i = 0.2 i out . the capacitor value and esr for output capacitor are estimated using the following equation: esr v esr i c out 1 v c 1 2 1 2f sw i 2 output ripple v pp v esr v c boost refer to application note an715 to determine the required inductance for a continuous conduction mode boost conversion. l min v 2 in d 2 f sw v out i out_min in a boost converter, entire load current is supplied by the output capacitor when the main switch is on. obviously, the output capacitance required to support the load is quite high, especially at a higher duty cycle. moreover, the output capacitor esr needs to be low enough for minimum voltage drop across it, while supporting the load. use the following equation to calculate the output capacitor, for a specified ripple performance. esr v esr i c out i out d max v c f sw output ripple v pp v esr v c where, l min = inductance required to remain in continuous conduction mode operation (h) d max = maximum duty cycle at minimum v in = converter efficiency i out_min = minimum output current for continuous conduction mode (a)
AN729 vishay siliconix document number: 71116 25-feb-00 www.vishay siliconix.com faxback 408-970-5600 7 use the following equations to calculate dc, peak, and rms values of currents in the n- and p-channel switches in buck or boost converter designs. figure 9. current waveform (buck, boost) i pch (buck), i nch (boost) i nch (buck), i pch (boost) i inductor (buck, boost) i i pk i dc i pk i dc i buck converter i v in v o d l f sw (2) d 1.05 v o v in i dc i o i 2 i pk i o i 2 (3) i rms p i 2 dc i 2 pk i dc i pk d 3 i rms n i 2 dc i 2 pk i dc i pk i d 3 boost converter i v in d f sw l (4) d 1.1 v o v in v o i dc i in i 2 i pk i in i 2 i rms_p i 2 dc i 2 pk i dc i pk 1d 3 i rms_n i 2 dc i 2 pk i dc i pk d 3 where, i = peak-to-peak ripple current (a) d = converter duty cycle i dc , i pk = refer to figure 9 i l = inductor current (a) i rms p , i rms n = rms current thru p, n-channel switch (a) f sw = converter switching frequency (hz)
AN729 vishay siliconix www.vishay siliconix.com faxback 408-970-5600 8 document number: 71116 25-feb-00

c3 0.1 f c2 22 f 16 v 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 si9168bq u1 1 v out 3.6 v 2.5 a c4 330 pf c8 0.1 f c6 1 n f c7 56 pf c5 0.1 f 3 7, 8 5, 6 2 c1 22 f 16 v r1* 51 r5 75 k r8* 2.7 r9* 2.7 4 r6 8.2 k q1b si9801dy q1a si9801dy r2 200 r3 22 k r4 12.4 k pwm/psm to v in for pwm mode; pwm/psm to gnd for psm mode. sd to v in for converter enable mode; sd to gnd for shutdown mode. * = optional l1, 1.5 h ihlp2525 d1 b130lb c9 0.1 f mode d l pgnd sd v out v dd r osc comp v s nc d h pwm/psm gnd v ref fb sync v in 5-10 v com com r1* 51 c3 0.1 f c2 10 f 10 v 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 si9168bq u1 2, 3 v in 5-10 v v out 3.6 v 1.5 a c4 330 pf c8 0.1 f c6 1 nf c7 56 pf c5 0.1 f 6, 7 8 1 4 c1 22 f 16 v r5 75 k r8* 5.6 r9* 5.6 5 r6 8.2 k q1b si6803dq q1a si6803dq r2 200 r3 22 k r4 12.4 k l1, 4.7 h ihlp2525 d1 mbr0520t1 c9 0.1 f mode d l pgnd sd v out v dd r osc comp v s nc d h pwm/psm gnd v ref fb sync com com pwm/psm to v in for pwm mode; pwm/psm to gnd for psm mode. sd to v in for converter enable mode; sd to gnd for shutdown mode. * = optional figure 10. 1.5a buck regulator using the si9168bq figure 11. 2.5a buck regulator using the si9168bq
AN729 vishay siliconix document number: 71116 25-feb-00 www.vishay siliconix.com faxback 408-970-5600 9 figure 12. 7.2-v o /2.5-a boost regulator application c1 10 f 16 v 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 u1 v in 5-7.2 v c2 47 f 16 v c3 0.1 f q1 si9803dy c4 560 pf c8 0.1 f c6 5.6 nf c7 220 pf c5 0.1 f 4 r1* 51 r5 75 k 1, 2, 3 r6 4.7 k r3 56.2 k r2 1 k r4 12.4 k 5, 6, 7, 8 3 4 1, 2, 5, 6 q2 si3442dv d1 b130lb l1, 1.5 h ihlp2525 si9168bq v out 7.2 v 2.5 a mode d l pgnd sd v out v dd r osc comp v s nc d h pwm/psm gnd v ref fb sync com com pwm/psm to v in for pwm mode; pwm/psm to gnd for psm mode. sd to v in for converter enable mode; sd to gnd for shutdown mode. * = optional
AN729 vishay siliconix www.vishay siliconix.com faxback 408-970-5600 10 document number: 71116 25-feb-00 figure 13. efficiencye1.5-a buck converter figure 14. efficiencyeboost converter 50 60 70 80 90 100 10 100 1000 10000 efficiency ebuck, v out = 3.6 v load current (ma) efficiency (%) psm = 5 v in pwm = 5 v in pwm = 7.2 v in psm = 7.2 v in psm = 8.4 v in pwm = 8.4 v in 50 60 70 80 90 100 10 100 1000 10000 efficiency eboost, v out = 7.2 v load current (ma) efficiency (%) psm = 7.0 v in psm = 5.4 v in psm = 6.0 v in pwm = 5.4 v in pwm = 6.0 v in pwm = 7.0 v in v in = 7.2 v, v o = 3.6 v slew rate 1a/ sec ch 3 load (1a/div) ch4 output (200 mv/div) figure 15. dynamic load response buck converter pwm v in = 7.2 v, v o = 3.6 v slew rate 1a/ sec ch 3 load (100 ma/div) ch4 output (100 mv/div) figure 16. dynamic load response buck converter psm v in = 5.4 v, v out = 7.2 v slew rate 1a/ sec ch 3 load (1a/div) ch4 output (200 mv/div) figure 17. dynamic load response boost converter pwm v in = 5.4 v, v out = 7.2 v slew rate 1a/ sec ch 3 load (200 ma/div) ch4 output (50 mv/div) figure 18. dynamic load response boost converter psm

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